本书主要介绍数字系统设计的基本原理。VHDL是一种设计语言，这种设计语言允许设计人员先对基本的数字电路的特性和结构建模，然后再自动实现高级描述的电路结构。全书共分12章，主要讨论了电路设计自动工具的使用、CMOS和可编程逻辑技术，布尔代数的原理和组合逻辑设计。全书通过基本逻辑门模型引入了VHDL，强调了文档化代码的重要性，同时描述了各种建模技术，有限状态机的设计等。本书适合于学习数字电路课程的学生和相关工程技术人员。
目 录
Preface
1Introduttion
1.1Moderndigitaldesign
1.2CMOStechnology
1.3Programmablelogic
1.4Electricalpropenies
1.5Summary
1.6Funherreading
Exercises
2Combinationallogicdesign
2.1Booleanalgebra
2.2Logicgates
2.3Combinationallogicdesign
2.4Timing
2.5Numbercodes
2.6Summary
2.7Funherreading
Exercises
3CombinationallogicusingVHDLgatemodels
3.1Entitiesandarchitectures
3.2Identifiers,spacesandcommenb
3.3Netlists
3.4Signalassignments
3.5Generics
3.6Constantandopenpons
3.7Testbenches
3.8Configurations
3.9Summary
3.10Funherreading
Exercises
4Combinatlonalbuildingblocks
4.1Three-statebuffers
4.2Decoders
4.3Multiplexers
4.4Priorityencoder
4.5Adders
4.6Paritychecker
4.7Summary
4.8Furtherreading
Exercises
5Synchronoussequentialdesign
5.1Synchronoussequentialsystems
5.2Modelsofsynchronoussequentialsystems
5.3Algorithmicstatemachines
5.4SynthesisfromASMcharts
5.55tatemachinesinVHDL
5.6Summary
5.7Funherreading
Exercises
6VHDLmodelsofsequentlallogicblocks
6.1Latches
6.2Flip-fiops
6.3JKandTflip-flops
6.4Registersandshiftregisters
6.5Counters
6.6Memory
6.7Sequentialmultiplier
6.8Summary
6.9Funherreading
Exercises
7Complexsequentialsystems
7.1Linkedstatemachines
7.2Datapath/controllerpanitioning
7.3Instructions
7.4Asimplemicroprocessor
7.5VHDLmodelofasimplemicroprocessor
7.6Summary
7.7Futherreading
Exercises
8VHDLsimulation
8.1Event-drivensimulation
8.2SimulationofVHDLmodels
8.3Simulationmodellingissues
8.4Fikeoperations
8.5Summary
8.6Funherreading
Exercises
9VHDLsynthesls
9.1RTLsynthesis
9.2Constraints
9.3SynthesisforFPCAs
9.4Behaviouralsynthesis
9.5Summary
9.6Futherreading
Exercises
10Testingdigitalsystems
1O.1Theneedfortesting
10.2Faultmodels
10.3Fault-orientedtestpatterngeneration
10.tFaultsimulation
10.5FaultsimulationinVHDL
10.6Summary
10.7Furtherreading
Exercises
11Designfortestability
11.1Adhoctestabilityimprovements
11.2Structureddesignfortest
11.3Built-inself-test
11.4Boundaryscan(IEEE1149.1)
11.5Summary
11.6Furtherreading
Exercises
12Asynthronoussequentialdesign
12.1Asynchronouscircuib
12.2Analysisofasynchronouscircuits
12.3Designofasynchronoussequentialcircuits
12.4Setupandholdtimesandmetastability
12.5Summary
12.6Furtherreading
Exercises
Appendices
AVHDLstandards
BVerilog
C1076A-sharedvariables
Bibliography
Answerstoselectedproblems
Index
装 帧：平装
页 数：618
版 次：1版
开 本：64
正文语种：葡萄牙语/英语
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